The Mighty Ramp
Designed by Zak W
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Page last updated 6.5.2026
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The Mighty Ramp v1.0 PCB and 3D printed base
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Project Overview
Project Overview
The Mighty Ramp is a passion project that I have been working on and off for around 9 months as of June 2026. I built it as a way to give back to the SSTC community and help people getting into the high-voltage hobby who may not know which designs actually work well, what is reliable, or how to avoid the common failures that so many older SSTC designs suffer from. A lot of the popular SSTC schematics floating around are over 10 years old, and it often feels like once people move on to DRSSTCs and QCWs, beginner SSTCs get left behind without much improvement or modernization.
The goal of the Mighty Ramp was to take what I learned from building coils over the years and create a more robust, modern SSTC driver. It utilizes a compact 4-layer PCB, modern SMD components, and protection features like under-voltage lockout (UVLO) and over-current protection (OCP), borrowed from DRSSTC drivers, to help prevent accidental failures and make the coil more reliable overall.
This is only Version 1.0, and I expect the project to continue to evolve over time.
30" arc from a 5in tall secondary coil, 80A primary current
Mighty Ramp driver & Half Bridge
Features
Features
Using a half bridge, output can reach at least 30in (76cm) or more when tuned correctly.
Produces quiet, long sword arcs using the natural mains half cycle.
Secondary base current feedback for single resonant operation.
Powerful gate drive, capable of driving a half or full bridge.
Reliable startup via injection-locked oscillator.
Compact 4-layer PCB, only 60×60mm.
Primary feedback for OCP.
OCP & UVLO protection.
The Mighty Ramp SSTC is a compact single-resonant driver designed to power either a half-bridge or full-bridge to produce sword-like arcs. It includes features aimed at improving stability and robustness compared to many existing SSTC drivers. For tracking the AC half-cycle, the driver requires the bridge to be powered from a level-shifted doubler to produce 340 VDC peak ramps (120 VAC input).
The DC sense circuit and staccato interrupter enable the coil just as the doubled half-wave ramp starts. As a result, an arc is formed and continues to grow as the ramp voltage increases. Secondary base feedback via a CT is paired with an injection-locked self-oscillator to ensure reliable startup and operation. The oscillator frequency is manually adjusted with an onboard trimmer potentiometer to be close to the secondary's resonant frequency. At the beginning of each ramp half-cycle, the oscillator starts the bridge switching until a strong enough signal is produced by the secondary feedback CT. Once this occurs, the secondary feedback overrides the self-oscillation and locks onto the secondary's resonant frequency.
The controller also provides overcurrent protection to shut down the driver if primary current exceeds the set threshold. The driver supports either an onboard 1:20 SMD CT, so only a low-turn external CT is needed, or two external cascaded CTs. UVLO is also built in to disable the driver if the 20 V rail drops below a set threshold, ensuring the bridge shuts off safely.
The controller is powered directly from an SMPS with an input range of 16-24 V, depending on how hard you want to drive the FETs. Gate drive is handled by two IXDD609SIA ICs. Each can operate up to 35 V and sink 9 A peak, making them well suited for driving a half-bridge or full-bridge.
Driver Overview
Driver Overview
OCP/UVLO Indicator - An onboard LED that indicates when overcurrent protection OCP or UVLO has been triggered. When first powering on the board, the LED can be lit; this is normal. The driver is enabled by the rising edge of the interrupter. The driver must be connected to Vbus+ / Vbus- with power on in order to sense the AC half-cycle and output an interrupter pulse to clear the OCP/UVLO. See Powering the Driver notes below for more information.
Interrupter - An onboard LED that indicates when the interrupter outputs an enable signal.
Power Indicator - An onboard LED that indicates when the driver is powered on.
GDT Primary Output - Connects to the gate driver transformer (GDT) primary to drive the bridge. If the bridge does not oscillate, swapping the phase may be required. See Gate Driver Transformer notes below for more information.
UVLO Setpoint - Adjusts the threshold for when UVLO is triggered. See UVLO notes below for more information.
Oscillator Adjustment - Adjusts the self-oscillator frequency. This should be checked when first powering on the driver. See Injection-Locked Oscillator notes below for more information.
OCP Setpoint Adjustment - Adjusts the threshold for when OCP triggers and disables the driver. See OCP notes below for more information.
BPS Adjustment Header - Adjusts interrupter beats per second (BPS), 1-30Hz.
SEC FB (Header) - Input for the secondary feedback CT. See Secondary Feedback notes below for more information.
PRI FB (Header) - Input for the primary OCP CT. See Primary CT notes below for more information.
DC Input (Header) - DC input for powering the driver. See Powering the Driver notes below for more information.
Bridge PWR (Header) - Vbus+ and Vbus- connection from the bridge to the driver. See Connecting the Driver to the Bridge notes below for more information.
Test Points: See Test Points & Example Waveforms notes for more information.
Interrupter Test (TP4) - Test point for probing the interrupter output.
Secondary CT Feedback Test (TP5) - Test point for probing the secondary CT feedback.
Primary CT Test (TP1) - Test point for probing the primary CT.
OCP Setpoint (TP7) - Test point for measuring OCP threshold voltage. See Setting OCP notes below for more information.
UVLO Test (TP3) - Test point for measuring DC input voltage at U2B for determining UVLO trip voltage.
UVLO Setpoint Test (TP2) - Test point for measuring UVLO threshold voltage. See Setting UVLO notes below for more information.
Feedback & Oscillator Test (TP6) - Test point for probing the self-oscillator frequency and secondary feedback (once the driver is locked onto the secondary feedback).
Schematic
Schematic
High resolution version available below in Downloads.
Gate Drive Transformer (GDT)
Gate Drive Transformer (GDT)
The GDT is a critical part of the project; care should be taken when constructing it. I would recommend following this guide on how to construct one. It is important that the leads coming off the GDT are twisted together and kept relatively short between the driver and bridge in order to reduce leakage inductance. Be sure to note the phase of the leads before twisting them and trimming the ends to match.
I have tested both of these N87 ferrite cores with the driver:
B64290L0618X087 - 25.3X14.8X10 N87 TOROID (larger)
B64290L0632X087 - 20X10X7 N87 TOROID (smaller)
If using a larger core, like the B64290L0618X087 mentioned above, I would recommend 5-6 turns.
If using the smaller core, like the B64290L0632X087 mentioned above, I would recommend 7 turns.
20X10X7 N87 TOROID (smaller) with 7 turns
25.3X14.8X10 N87 TOROID (larger) with 5 turns
Injection locked oscillator
Injection locked oscillator
In order for the driver to run reliably, an injection-locked oscillator (self-oscillation) is used. The components around U2C are selected in order to let the oscillator run from around 300 kHz-650 kHz continuously, even when the bridge is not powered on. An important step in setting up the driver is to make sure the oscillator is adjusted using the 50 kΩ potentiometer (RV1) so that the frequency is close to (slightly above or below) the secondary's resonant frequency. Fine adjustment is not required.
The oscillator performs two functions:
Reliable operation of the coil and triggering of the driver. Since a mains-ramped coil takes advantage of the natural AC half-cycle (see Half-Wave Doubler section below), at the start of the half-cycle the bridge sees a low voltage, which can cause little to no feedback for the driver. Therefore, the oscillator is used to kick-start this process. Even at an initially low bus voltage, the oscillator will allow the bridge to start switching. After a very short period [insert time here], the feedback is strong enough to override the oscillator, allowing the driver to run at the secondary's natural resonant frequency throughout the remaining duration of the half-cycle.
Easy testing of the driver and bridge gate signal. Testing the GDT and scoping the bridge Vge (gate and emitter) signal. Since the driver is always running due to the oscillator, simply connecting the driver to the output of the level-shifted doubler (Vbus+ and Vbus-) will allow the driver to track the AC cycle and enable the driver output without feedback. This allows the bridge Vge (gate and emitter) signal to be tested to ensure it looks correct. While this test alone, without powering the bridge, is not always indicative of how the gate signal will look while the bridge is powered on, it can be a good step to ensure the driver and GDT are working correctly. See [bridge section or powering the driver] below for more information.
Secondary Feedback CT
Secondary Feedback CT
The driver receives feedback via a single CT with a ratio of 3:30. While the exact ratio is not required, that is what I recommend. Instead of most designs that use a single secondary turn as it passes through the CT, the Mighty Ramp increases feedback current to around 100mA using the 3 turns on the CT.
If you'd like to measure the secondary feedback current, use a ratio of 1:10 instead of 3:30. See Measuring Secondary and Primary Current notes below for more information.
I have tested both of these N87 ferrite cores for secondary feedback:
B64290L0618X087 - 25.3X14.8X10 N87 TOROID (larger)
B64290L0632X087 - 20X10X7 N87 TOROID (smaller)
Secondary feedback CT using the 20X10X7 N87 TOROID (smaller) core
Primary OCP CT
Primary OCP CT
The driver supports either an onboard 1:20 SMD CT or two external cascaded CTs. If using the onboard SMD CT (53020C), then only a single external CT is needed. I recommend using 10 turns on an N87 type core or similar.
If not using the onboard SMD CT, then the jumper (JP1), located on the bottom of the PCB, needs to be bridged. Then two CTs can be cascaded together using the same turn ratio as before, 1:10:20 (200 turns). The ratio is not critical, but 1:200 provides a wide range for adjustment while also staying within the recommended range of 500mA-1A of feedback current.
The Vbus- connection of the primary wire is passed through the center of the CT.
I have tested both of these N87 ferrite cores for the primary CT:
B64290L0618X087 - 25.3X14.8X10 N87 TOROID (larger)
B64290L0632X087 - 20X10X7 N87 TOROID (smaller)
Using the onboard SMD CT, a single 10 turn CT is used
Without the SMD CT, two casscaded CTs are required. 1:10:20
Setting OCP
Setting OCP
When first testing the driver and bridge, I recommend setting OCP to a lower value before testing the bridge at full power. I have run my half-bridge up to 90 A using a pair of FGH75T65S IGBTs. That is not the limit for these devices, but given the fixed ramp time of the half-wave doubler, the arcs can start to branch more as current is increased.
Using the above formula, the approximate voltage that U2A will see on the inverting input (pin 2) after R33 can be calculated. As an example for testing the bridge, OCP could be set to only 40A, which would equate to 1V. Using the OCP setpoint test point (TP7), the voltage on pin 3 can be measured and adjusted using RV2.
With the OCP voltage set and the OCP CT connected to the driver, it will now shut down the gate drive during the half-cycle, only resetting until the next rising edge of the interrupt pulse. See Flip-flop Latch notes below for more information.
Setting UVLO
Setting UVLO
Determining the UVLO threshold voltage:
With the driver powered on, measure the voltage at the UVLO setpoint (TP2) and UVLO test point (TP3). Adjust RV6 until the voltage measured at UVLO test point (TP3) is greater than the voltage at pin 5 (TP3).
Using an adjustable power supply, set the voltage to the desired lockout voltage. For example, I used 18V for my threshold voltage. With the power supply adjusted to the desired lockout voltage, remeasure UVLO test point (TP3). Note the voltage.
Now increase the driver voltage back to the desired operating voltage. 20VDC is recommended.
Adjust UVLO setpoint (TP2) voltage using RV6 to the noted voltage.
Test the UVLO by decreasing the voltage to the driver. Once it drops below the target value, the OCP/UVLO indicator LED will trip, signifying UVLO has occurred, at which point the driver is disabled.
Note: when powering down the driver, it is normal for the LED to illuminate as the driver loses power.
Flip-flop Latch
Flip-flop Latch
In order for an OCP & UVLO event to disable the driver, a 74LVC2G74DP flip-flop (U7) is used. Simply configured as a latch, it is able to disable the gate driver ICs via Q1 and hold them low.
When either event is triggered, Q̅ (pin 3) goes HIGH. As a result, Q1 pulls the enable pins of the gate driver ICs low, disabling the driver until the latch is reset.
A reset occurs during the rising edge of the interrupter pulse. This ensures the coil remains off for the remainder of the half-cycle, only re-enabling the driver at the start of a new half-cycle.
DC Sense & Staccato Interrupter
DC Sense & Staccato Interrupter
In order for the driver to enable the bridge at the beginning of the ramp, the output of the doubler is connected to the driver through a reverse-biased high-voltage diode (D3). Here is how the DC sense circuit and interrupter work together to track the half-cycle and enable the bridge at the correct time.
The driver outputs an initial enable pulse at the beginning of the half-cycle as the bus voltage starts to increase. This causes D3 to become reverse-biased. At this time, the voltage at pin 1 of U3A increases from 0V and is held around 5V due to the resistor divider R5, R7, and R4 (green waveform below).
At the end of the half-cycle, the doubler voltage drops towards zero, causing D3 to become forward-biased and conduct. This decreases the voltage after the resistor divider R5, R7, and R4 (green waveform below). D3 becomes reverse-biased again once the next positive half-cycle starts . This change in voltage causes the Schmitt trigger U3A to output an inverted signal (teal waveform below).
The interrupter then disables the output for several cycles by holding the output of U3A, after R18, HIGH through D7.
After a short delay (set by the BPS potentiometer), the interrupter then pulls the node LOW for the duration of the half-cycle, triggering a HIGH output from the second inverting stage (U3C) before returning HIGH again after the half-cycle ends.
Finally, the signal is inverted once again before driving Q1. The output of Q1 is inverted, thus ensuring the interrupter signal is in sync with the positive half-cycle.
Example LTspice simulation below.
Since the output from the doubler needs to be connected to the driver it is critical to verify the outlet wiring to ensure HOT and NEUTRAL are wired correctly. If not, the doubler, driver, and bridge could become live and will be a shock hazard.
The AC input voltage was adjusted from 170V to 25V to make the other waveforms easier to see.
LTspice simulation capture: Blue trace = Doubler_Vbus+ output, green = pin1 of the schmitt trigger, teal = output of the first schmitt trigger, red = the interrupter signal that is sent to the gate drive ICs
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