The Mighty Ramp

Page last updated 6.21.2026

The Mighty Ramp v1.0 PCB and 3D printed base

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Project Overview

WARNING: This project involves working with mains voltage and high voltage capacitors, which can cause serious injury or death. High voltage capacitors may retain a dangerous charge even after power is disconnected. Only attempt this project if you understand the associated hazards and proper safety procedures. Proceed at your own risk.

The Mighty Ramp is a passion project that I have been working on and off for around 9 months as of June 2026. It is my way of giving back to the SSTC community and helping others get into the high-voltage hobby.

Over the years, I have spent countless hours Googling issues, troubleshooting circuits to no end, and asking for help on online forums. After building several coils and learning what works and what doesn't, I decided to build the Mighty Ramp as a more reliable alternative to older SSTC designs.

For many people, an SSTC is a rite of passage into the high voltage hobby. They are fun circuits to build and can produce impressive arcs, but their simple designs are often fragile and prone to failure. The goal of the Mighty Ramp was to take what I learned over the years and create a more robust, modern SSTC driver. It borrows many of the features commonly found on DRSSTC drivers, including under voltage lockout (UVLO) and over current protection (OCP), providing guardrails that help prevent failures, saving time and money that would otherwise be spent replacing broken parts.

The PCB is designed to be compact and uses modern SMD components on a 4-layer board. The result is a driver that not only addresses many of the common failure modes found in traditional SSTCs but also reduces problems caused by poor layout, part selection, and construction.

This is only Version 1.0, and I expect the project to continue evolving over time.

30" arc from a 4in tall secondary coil, 80A primary current

Mighty Ramp driver & Half Bridge

Features

Using a half bridge, output can reach at least 30in (76cm) or more when tuned correctly from a 120VAC supply.
Produces quiet, long sword arcs using the natural mains half cycle.
Secondary base current feedback for single resonant operation.
Powerful gate drive, capable of driving a half or full bridge.
Reliable startup via injection-locked oscillator.
Compact 4-layer PCB, only 60×60mm.
Primary feedback for OCP.
OCP & UVLO protection.

The Mighty Ramp SSTC is a compact single resonant driver designed to power either a half or full bridge to produce sword like arcs. It includes features aimed at improving stability and robustness compared to many existing SSTC drivers. For tracking the AC half-cycle, the driver requires the bridge to be powered from a level shifted doubler to produce 340VDC peak ramps (120VAC input).

The DC sense circuit and staccato interrupter enable the coil just as the doubled half-wave ramp starts. As a result, an arc is formed and continues to grow as the ramp voltage increases. Secondary base feedback via a CT is paired with an injection-locked self oscillator to ensure reliable startup and operation.

At the beginning of each ramp half-cycle, the oscillator starts the bridge switching until a strong enough signal is produced by the secondary feedback CT. Once this occurs, the secondary feedback overrides the self oscillation and locks onto the secondary's resonant frequency.

The driver also provides overcurrent protection to shut down the driver if the primary current exceeds the set threshold. The driver supports either an onboard 1:20 SMD CT, so only a low-turn external CT is needed, or two external cascaded CTs. UVLO is also built in to disable the driver if the 20V rail drops below a set threshold, ensuring the bridge shuts off safely.

The controller is powered directly from an SMPS with an input range of 16-24V, depending on how hard you want to drive the bridge. Gate drive is handled by two IXDD609SIA ICs. Each can operate up to 35V and sink 9A peak, making them well suited for driving a half- or full-bridge.

Driver Overview

OCP/UVLO Indicator - An onboard LED that indicates when OCP or UVLO has been triggered.

Note: When first powering on the board, the LED can be lit, this is normal. The driver is enabled by the rising edge of the interrupter. The driver must be connected to Vbus+ / Vbus- with power on in order to sense the AC half-cycle and output an interrupter pulse to clear the OCP/UVLO. See Driver setup notes below for more information.

Interrupter - An onboard LED that indicates when the interrupter outputs an enable signal.

Power Indicator - An onboard LED that indicates when the driver is powered on.

GDT Primary Output - Connects to the gate driver transformer (GDT) primary to drive the bridge. If the bridge does not oscillate, swapping the phase may be required. See Adjusting GDT Phase notes below for more information.

UVLO Setpoint - Adjusts the threshold for when UVLO is triggered. See Setting UVLO notes below for more information.

Oscillator Adjustment - Adjusts the self oscillator frequency. This should be checked when first powering on the driver. See Injection locked oscillator notes below for more information.

OCP Setpoint Adjustment - Adjusts the threshold for when OCP triggers and disables the driver. See Setting OCP notes below for more information.

BPS Adjustment Header - Adjusts interrupter beats per second (BPS), 1-30Hz. See DC Sense & Staccato Interrupter notes below for more information.

SEC FB (Header) - Input for the secondary feedback CT. See Secondary Feedback CT notes below for more information.

PRI FB (Header) - Input for the primary OCP CT. See Primary OCP CT notes below for more information.

DC Input (Header) - DC input for powering the driver. See Driver setup notes below for more information.

Bridge PWR (Header) - Vbus+ and Vbus- connection from the bridge to the driver. See DC Sense & Staccato Interrupter notes below for more information.

JP1 (backside of PCB) - Solder jumper for configuring the driver to use either the onboard SMD CT or two cascaded CTs for OCP. Open = onboard CT + a single 10 turn CT, closed = using two external CTs. See Primary OCP CT notes below for more information.

Mounting Holes - M3 size bolts are used for mounting the PCB. All of the mounting holes are grounded and can be used for grounding your scope probe.

Test Points: See Test Points & Example Waveforms notes for more information.

Interrupter Test (TP4) - Test point for probing the interrupter output.
Secondary CT Feedback Test (TP5) - Test point for probing the secondary CT feedback.
Primary CT Test (TP1) - Test point for probing the primary CT.
OCP Setpoint (TP7) - Test point for measuring OCP threshold voltage. See Setting OCP notes below for more information.
UVLO Test (TP3) - Test point for measuring DC input voltage at U2B for determining UVLO trip voltage.
UVLO Setpoint Test (TP2) - Test point for measuring UVLO threshold voltage. See Setting UVLO notes below for more information.
Feedback & Oscillator Test (TP6) - Test point for probing the self oscillator frequency and secondary feedback (once the driver is locked onto the secondary feedback). See Injection locked oscillator notes below for more information.

Schematic

High resolution versions available below in Downloads.

Gate Drive Transformer (GDT)

The GDT is a critical part of the project; care should be taken when constructing it. I would recommend following this guide on how to construct one. It is important that the leads coming off the GDT are twisted together and kept relatively short between the driver and bridge in order to reduce leakage inductance.

Be sure to note the phase of the leads before twisting them and trimming the ends to match.

I have tested both of these N87 ferrite cores with the driver. Either can be used without issues.

B64290L0618X087 - 25.3X14.8X10 N87 TOROID (larger)
B64290L0632X087 - 20X10X7 N87 TOROID (smaller)

If using a larger core, like the B64290L0618X087 mentioned above, I would recommend 5-6 turns.

If using the smaller core, like the B64290L0632X087 mentioned above, I would recommend 7 turns.

Adjusting GDT Phase

In order for the bridge to oscillate correctly, the phase of the GDT and/or secondary feedback CT may need to be adjusted.

The phase of the GDT can be easily changed by using the terminal connection on the PCB. Simply unscrew the GDT primary wires and swap them around to change the phase.

20X10X7 N87 TOROID (smaller) with 7 turns

25.3X14.8X10 N87 TOROID (larger) with 5 turns

GDT secondary outputs that connect to the bridge (red and purple twisted pair).

Primary input that connects to the driver screw terminal block (grey twisted pair).

Secondary Feedback CT

The driver receives feedback via a single CT with a ratio of 3:30. While the exact ratio is not required, that is what I recommend. Instead of most designs that use a single secondary turn that passes through the CT, the Mighty Ramp increases feedback current to around 100mA using the 3 turns on the CT.

I have tested both of these N87 ferrite cores for secondary feedback: Either can be used without issues.

B64290L0618X087 - 25.3X14.8X10 N87 TOROID (larger)
B64290L0632X087 - 20X10X7 N87 TOROID (smaller)

Secondary Feedback Phasing

In order for the bridge to oscillate correctly, the phase of the GDT and/or secondary feedback CT may need to be adjusted.

The phase can be adjusted a few ways depending on how you have wired your CT and secondary ground wire. In the photo of the secondary feedback CT, I used terminal blocks, which allow the input and output of the CT to be easily adjusted.

Phase is determined by the direction that the secondary ground wire passes through the CT. If the phase is not correct, try changing the winding direction by rewinding the three turns on the CT in the opposite direction.

Secondary feedback CT using the 20X10X7 N87 TOROID (smaller) core

Primary OCP CT

The driver supports either an onboard 1:20 SMD CT or two external cascaded CTs. If using the onboard SMD CT (53020C), then only a single external CT is needed. I recommend using 10 turns on an N87 type core or similar.

If not using the onboard SMD CT, then the jumper (JP1), located on the bottom of the PCB, needs to be bridged. Then two CTs can be cascaded together using the same turn ratio as before, 1:10:20 (200 turns). The ratio is not critical, but 1:200 provides a wide range for adjustment while also staying within the recommended range of 500mA-1A of feedback current.

The Vbus- connection of the primary wire should be passed through the center of the CT.

I have tested both of these N87 ferrite cores with the driver. Either can be used without issues.

B64290L0618X087 - 25.3X14.8X10 N87 TOROID (larger)
B64290L0632X087 - 20X10X7 N87 TOROID (smaller)

Using the onboard SMD CT, a single 10 turn CT is used

Without the SMD CT, two casscaded CTs are required. 1:10:20

Cascading two CTs together

Here is an example to clarify how two CTs are cascaded together. The ratio we are going for is 1:10:1:20, more commonly written as 1:10:20.

Starting from left to right, 1:10:1:20

1 = the single turn of the primary (Vbus-) that passes through the core of the 10 turn CT.
10 = the first CT with 10 turns wrapped around the core.
1 = A single turn from the 10 turn CT that is wrapped around the second CT in the cascade and soldered together to form 1 turn around the second CT.
20 = the second CT with 20 turns wrapped around the core. The output connects to the Primary OCP header on the driver.

Example of cascaded CTs

Example of the single turn connecting one CT to the other

The left CT has 20 turns. The right CT has 10 turns. The single turn that links the two CTs counts as the 10th turn for the right CT.

Setting OCP

When first testing the driver and bridge, I recommend setting OCP to a lower value before testing the bridge at full power. I have run my half-bridge up to 90A using a pair of FGH75T65S IGBTs. That is not the limit for these devices, but given the fixed ramp time of the half-wave doubler, the arcs can start to branch more as current is increased.

Note: At full BPS (30Hz), my coil pulls around 10A at 120VAC. Roughly 1.2kW of power.

Using the above formula, the approximate voltage that U2A will see on the inverting input (pin 2) after R33 can be calculated. As an example for testing the bridge, OCP could be set to only 40A, which would equate to 1V. Using the OCP setpoint test point (TP7), the voltage on pin 3 can be measured and adjusted using RV2.

With the OCP voltage set and the OCP CT connected to the driver, it will now shut down the gate drive during the half-cycle, only resetting until the next rising edge of the interrupter pulse. See Flip-flop Latch notes below for more information.

Setting UVLO

Determining the UVLO threshold voltage:

With the driver powered on, measure the voltage at the UVLO test point (TP3). At 20VDC this should measure around 3.33V.
Using an adjustable power supply, set the voltage to the desired lockout voltage. For example, I used 18V for my threshold voltage. With the power supply adjusted to the desired lockout voltage, remeasure UVLO test point (TP3).
While measuring the UVLO setpoint (TP2), use RV6 to match the voltage measured at the UVLO test point (TP3).
Now increase the driver voltage back to the desired operating voltage. 20VDC is recommended.

Test the UVLO by decreasing the voltage to the driver. Once it drops below the target value, the OCP/UVLO indicator LED will trip, signifying UVLO has occurred, at which point the driver is disabled. Increasing the voltage back to 20V will cause the LED to turn off. If it does not, the flip-flop latch will need to be reset by the interrupter.

- Note: when powering down the driver, it is normal for the LED to illuminate as the driver loses power.

Flip-flop Latch

In order for an OCP & UVLO event to disable the driver, a 74LVC2G74DP flip-flop (U7) is used. Simply configured as a latch, it is able to disable the gate driver ICs via Q1 and hold them low.

When either event is triggered, Q̅ (pin 3) goes HIGH. As a result, Q1 pulls the enable pins of the gate driver ICs low, disabling the driver until the latch is reset.

A reset occurs during the rising edge of the interrupter pulse. This ensures the coil remains off for the remainder of the half-cycle, only re-enabling the driver at the start of a new half-cycle.

Injection locked oscillator

In order for the driver to run reliably, an injection-locked oscillator (self oscillation) is used. The components around U2C are selected in order to let the oscillator run from around 200kHz-750kHz continuously, even when the bridge is not powered on. An important step in setting up the driver is to make sure the oscillator is adjusted using the 50kΩ potentiometer (RV1) so that the frequency is close to (slightly above or below) the secondary's resonant frequency. Fine adjustment is not required.

The oscillator performs two functions:

Reliable operation of the coil and triggering of the driver. Since a mains ramped coil takes advantage of the natural AC half-cycle (see DC Sense & Staccato Interrupter section below), at the start of the half-cycle the bridge sees a low voltage, which can cause little to no feedback for the driver. Therefore, the oscillator is used to kick start this process. Even at an initially low bus voltage, the oscillator will allow the bridge to start switching. After a very short period of around 200µs, the feedback is strong enough to override the oscillator, allowing the driver to run at the secondary's natural resonant frequency throughout the remaining duration of the half-cycle.
Easy testing of the driver and bridge gate signal. Since the driver is always running due to the oscillator, simply connecting the driver to the output of the level-shifted doubler (Vbus+ and Vbus-) will allow the driver to track the AC cycle and enable the driver output without feedback. This allows the bridge Vge (gate and emitter) signal to be tested to ensure it looks correct. While this test alone, without powering the bridge, is not always indicative of how the gate signal will look while the bridge is powered on, it can be a good step to ensure the driver and GDT are working correctly.

DC Sense & Staccato Interrupter

In order for the driver to enable the bridge at the beginning of the ramp, the output of the doubler is connected to the driver through a reverse-biased high voltage diode (D3). Here is how the DC sense circuit and interrupter work together to track the half-cycle and enable the bridge at the correct time.

The driver outputs an initial enable pulse at the beginning of the half-cycle as the bus voltage starts to increase. This causes D3 to become reverse-biased. At this time, the voltage at pin 1 of U3A increases from 0V and is held around 5V due to the resistor divider R5, R7, and R4 (green waveform below).
At the end of the half-cycle, the doubler voltage drops towards zero, causing D3 to become forward-biased and conduct. This decreases the voltage after the resistor divider R5, R7, and R4 (green waveform below). D3 becomes reverse-biased again once the next positive half-cycle starts. This change in voltage causes the Schmitt trigger U3A to output an inverted signal (teal waveform below).
The interrupter then disables the output for several cycles by holding the output of U3A (after R18) HIGH through D7.
After a short delay (set by the BPS potentiometer), the interrupter then pulls the node LOW for the duration of the half-cycle, triggering a HIGH output from the second inverting stage (U3C) before returning HIGH again after the half-cycle ends.
Finally, the signal is inverted once again before driving Q1. The output of Q1 is inverted, thus ensuring the interrupter signal is in sync with the positive half-cycle.

Example LTspice simulation below.

Since the output from the doubler needs to be connected to the driver, it is critical to verify the outlet wiring to ensure HOT and NEUTRAL are wired correctly. If not, the doubler, driver, and bridge could become live and present a shock hazard.

The AC input voltage was adjusted from 170V to 25V to make the other waveforms easier to see.

LTspice simulation capture: Blue trace = Doubler_Vbus+ output, green = pin 1 of the Schmitt trigger, teal = output of the first Schmitt trigger, red = the interrupter signal that is sent to the gate drive ICs.

Level Shifted Doubler

In order to get the longest arcs possible, the Mighty Ramp takes advantage of a level-shifted doubler (half-wave doubler) for a couple of reasons and requires it for the driver to track the mains half-cycle. See the DC Sense & Staccato Interrupter section above for more information.

The half-wave doubler not only increases the rectified AC peak voltage but also extends the ramp time as well. The RMS voltage of rectified 120VAC is 170VDC, where the positive half-cycle takes around 8.33ms (green waveform below). The doubler output peaks at 340VDC and extends the half-cycle ramp time to around 12.6ms. The increased peak bus voltage, in addition to the longer half-cycle time, allows for longer arcs.

Note: QCWDRSSTCs take advantage of this and use much longer ramp times to "grow" the arc over a longer period of time.

The output of the half-wave doubler naturally returns to zero volts after each half-cycle. The advantage of this is being able to use a larger bypass capacitor value (10-20µF) across Vbus+ and Vbus- on the half-bridge. This larger value helps to reduce switching spikes.

Other ramped coil designs (like my first RSSTC) that only use half-wave rectified AC require high-wattage bleed resistors to discharge the DC-link/bypass capacitors on the bridge after each cycle.

I tested the minimum capacitor value to be around 5,400µF before the arc length is impacted by not having enough stored energy during each burst. Going beyond that amount will help sustain arc length a bit at higher BPS. However, maximum BPS (30Hz) typically leads to shorter arcs due to previous arc paths heating the air near the breakout point.

**WARNING: A bleeder resistor should always be used across high voltage capacitors to drain them to a safe voltage before adjusting anything they are connected to**

LTspice simulation: Blue trace = output from level-shifted doubler, green trace = 170VAC.

Spice sine waves are defined by peak voltage, not RMS. So for simulation purposes, 170VAC was used instead of 120VAC.

Driver setup

Startup and shutdown sequence:

The driver should always be powered on first and shut down after the bridge.
- Note: While the driver has UVLO protection, it is possible for something to go wrong. If the driver loses power and gate drive is not disabled, the driver will try to drive the IGBTs as the 20VDC rail drops. If this occurs, the gate drivers could be running far below the optimal voltage the IGBTs require to switch safely and efficiently, which can lead to bridge failure.

Here is a high level breakdown of the steps that should be taken when testing the driver, doubler, and bridge:

Ensure the outlet wiring is correct and HOT and NEU are wired correctly.
Connect all external components via the headers on the PCB.
Check the driver DC power input with a multimeter to ensure there are no shorts on the DC power rail.
Power on the driver. The power LED should be on.

OCP/UVLO LED may also be on. This is normal. The flip-flop latch must receive a pulse from the interrupter in order to clear UVLO/OCP LED.

Using an oscilloscope, probe the Feedback & Oscillator Test Point (TP6) to measure and set the injection-locked oscillator to the correct unloaded frequency range of the secondary coil.

This does not have to be exact and only needs to be close to the resonant frequency (slightly above or below).

Use an oscilloscope to set the OCP & UVLO thresholds; see the OCP and UVLO sections above for these steps.
Keep the bridge disconnected from the half-wave doubler for this step. The PCB should be connected to the half-wave doubler (Vbus+ & Vbus-). A variac is recommended to increase the voltage slightly until the Interrupter LED begins to flash.
Verify the low-side IGBT gate signal (Vge) looks correct. At this point, the driver is not receiving any feedback from the coil, so the gate signal will be switching at the same frequency the injection-locked oscillator is running at. See Low Side IGBT Gate Waveform below for more information.

Probing the high-side IGBT is NOT recommended unless using a differential probe. If the low-side IGBT gate signal looks good, it can be assumed the high-side also matches since the GDT output is symmetrical.

If everything looks correct, turn off power to the half-wave doubler and driver. Connect the doubler to the bridge Vbus+ and Vbus-.

WARNING: A bleeder resistor should always be used across high voltage capacitors to drain them to a safe voltage before adjusting anything they are connected to. Exercise caution when connecting the doubler output to the bridge after powering it on, as the capacitors could be at a dangerous voltage.

You are now ready to power on the bridge and test the coil. Power on the driver and slowly increase the voltage with the variac until the Interrupter LED starts flashing.

If the phasing of the GDT and secondary feedback CT is correct, the coil might not output anything until a minimum voltage is reached with the variac (~30-50VAC).
If the coil is not oscillating and there is no output, DO NOT keep increasing the variac voltage. Instead, try changing one of these two things:
- Swap the GDT phase using the GDT terminal block on the PCB.
- Swap the secondary feedback CT phase by changing the winding direction of the secondary wire. See the Secondary Feedback CT section above for more information.

Congratulations! You can now start experimenting with tuning the coil to achieve the desired output.

If OCP was set to a lower current for testing, it may trip as you adjust the coupling, number of primary turns, or increase the bus voltage. Increase the OCP threshold if necessary.

Grounding

A few considerations for grounding the driver, half-wave doubler, and secondary coil.

Ensure the outlet wiring is correct and HOT and NEU are wired correctly.

Secondary Coil: The secondary coil should be connected to mains ground or earth.

Note: I have not had an issue grounding my SSTCs to mains ground. A direct earth connection can be used instead, or a large counterpoise ground can also be substituted.

The driver: The driver is grounded through the Vbus- connection (header) from the driver to the doubler/bridge.

Vbus- (neutral) is connected to ground back at the main breaker.

The Half-wave doubler: The doubler is only connected to HOT and NEU. Mains ground is used to ground the secondary coil.

The Bridge: The bridge is connected to Vbus+ and Vbus-.

The heatsink(s) should not be left floating, connect it to Vbus-.

Measuring Secondary & Primary Current

Both the secondary base current and primary current can be measured using the following formula with only slight differences.

Secondary Base Current

The CT voltage of the secondary feedback can be measured by probing the Secondary CT Feedback Test Point (TP5). The CT voltage can then be used in conjunction with the burden resistance and CT turn ratio, 1:10, not 3:30.

Note: 3:30 is used to increase the feedback current for the driver, but when calculating the secondary base current, 1:10 is used to derive the actual current.

Example based on Secondary CT Feedback Test Point (TP5) section below.

(8.6V x 10 turns) / 75Ω = 1.1A

Secondary feedback voltage

Primary Current

Calculating primary current follows the same process. Start by probing the Primary CT Test Point (TP1). Peak current is typically the critical metric to track, so make sure to measure at the peak of the burst on the oscilloscope.

Example based on Primary CT Test Point (TP1) section below.

(1.64V x 200 turns) / 5Ω = 65.6A

Primary CT voltage

Test Points & Example Waveforms

UVLO Test (TP3) & UVLO Setpoint Test (TP2):

Yellow = UVLO Test Point
Purple = UVLO Setpoint

With the driver running at 20VDC, the UVLO Test Point voltage reads 3.36V due to the resistor divider. The UVLO Setpoint reads 2.96V and has been adjusted with the UVLO ADJ potentiometer (RV6). When the UVLO Test Point voltage drops below this threshold (2.96V), the driver will be disabled.

OCP Setpoint (TP7):

Yellow = OCP Setpoint voltage

The OCP voltage is set at 2.24V or 89.6A. If this threshold is exceeded by the primary CT feedback signal, the driver will be disabled until the next interrupter cycle.

Secondary CT Feedback Test Point (TP5):

Purple = Secondary feedback CT

The secondary current waveform looks very similar to primary current because it also increases as the ramp voltage increases until reaching a peak in the middle of the cycle before returning to zero as the voltage ramps down.

Peak secondary feedback CT voltage was 8.6V or 1.1A

Feedback & Oscillator Test Point (TP6):

Yellow trace = The injection locked oscillator
Purple = Secondary feedback CT

This capture shows the injection-locked oscillator running at 431kHz just before the burst starts.
The entire burst end-to-end.
Zoomed-in capture right at the peak of the burst. Here we can see that the coil is running at 347kHz, not 431kHz. This is because the driver locked onto the secondary feedback signal from the CT early in the cycle.
Here we can see the very start of the burst (purple trace) with a small dip. This is where the injection-locked oscillator is being overridden by the secondary feedback signal from the coil. This happens around ~200µs into the cycle.

1. Free running injection locked oscillator. Running at 431kHz

2. The entire burst

3. Zoomed-in at the peak of the burst

4. Driver locking onto feedback signal around 200µs

Primary CT Test Point (TP1):

Yellow trace = primary current during a burst.

Zooming into the middle of the burst, peak current can be measured. Peak primary CT voltage was 1.64V or 65.6A.

Note: The primary current increases until halfway through the burst; this is when the half-wave ramp is at its peak voltage. As the ramp voltage decreases, so does the primary current.

Peak primary CT voltage was 1.64V or 65.6A

Interrupter Test Point (TP4):

Yellow trace = Interrupter output
Purple trace = Secondary Feedback CT

Here you can see the coil is ENABLED for the duration of the interrupter pulse.

Low Side IGBT Gate Waveform:

Yellow = Low side IGBT gate & emitter (Vge).

While the half bridge is not covered on this page, I wanted to include an example of what the gate waveform should look like. This is using the Mighty Ramp Half Bridge PCB while the bridge is powered.

Note: The negative peak is caused by the reverse diode across the 10Ω gate resistor for faster shutoff. This is normal and not an issue.

Secondary Size and Resonant Frequency

In order to produce straight sword arcs, a secondary with an unloaded resonant frequency of 300kHz or higher should be used. In my experience, a bit higher is better so that when the secondary is loaded down by the topload and arc, you are still above 300kHz.

Note: The secondary I used for this project runs around 400kHz unloaded and around 360kHz loaded.

I would recommend using a tool like JavaTC to calculate a secondary that will be within a similar range. SSTCs are typically designed to be around 1:1.5 to 1:2 aspect ratios, but this isn't a requirement.

Note: The coil I used for my project was 4in tall with a 3.75in diameter (really close to a 1:1 ratio). I also like to 3D print a custom shell that I add epoxy to in order to protect the secondary from primary to secondary flashovers. The epoxy does lower the resonant frequency by a lot, so a coil made with these same dimensions would have a higher resonant frequency than without the epoxy.

Ordering the PCB or PCBA

Note: I have only ordered these PCBs from JLCPCB.

The production files below in File Downloads contain all the required files to order the PCB as well as a partial assembly by JLCPCB.

I created these files with the KiCad plugin KiCad JLCPCB Tools by Bouni.

Ordering blank PCBs:

- Follow JLCPCB's upload process and upload the Gerber files.
- Customize your order however you like (I ordered everything with JLCPCB's defaults).
- Double check everything looks correct in the preview screen.
- If you are soldering all the components by hand, I highly recommend including a stencil.
- Save to cart.
  - You should have the PCBs and stencil in your cart ready to order.

Ordering partially assembled PCBs (PCBA) with basic components:

After uploading the Gerber files, select "PCB Assembly" at the bottom of the page.

- - Topside only
  - PCBA type = Economic
  - Everything else was left as default

Select Next.
Go to the "Bill of Materials" page.
Upload both the BOM.csv and the CPL.csv.
The part placement (IC orientation) should already be correct, since I updated them myself. If you notice an error, be sure to rotate the IC to correct the part placement, although this shouldn't be necessary.
Process BOM and CPL.
Choose which parts you want JLC to add. This should be all of them.
- Lib type should be Basic for all parts. Extended parts cost extra and have additional fees. The files were created to have only the Basic parts installed. If something has changed, specific parts can be adjusted using the edit icon. Search for a new Basic part that is compatible in LCSC and update the part number.
Select Next and double check component placement.
Next, save to cart.
- After this, you should have two separate items in your cart: the PCBs and the PCBAs.

JLC PCBA with basic components

File Downloads

If you build the Mighty Ramp and would like me to feature your build on my website, please email me photos of it.

Schematic v1.0 .png - High resolution schematic
Schematic v1.0 .pdf - High resolution PDF
PCB Layer Stackup .pdf - PDF export from KiCad of the layer stackup
Mighty Ramp v1.0 BOM - Google Sheets BOM
Mouser Shopping Cart - Full PCB shopping cart
Interactive BOM .html - Interactive BOM for assembling the PCB
Mighty Ramp v1.0 KiCad 9.0 Project Files .zip - All KiCad files
Mighty Ramp v1.0 Production Files .zip - All production files for ordering the PCBs
Mighty Ramp v1.0 PCB Base .3mf - 3D print file for mounting the PCB to a base (uses M3 brass threaded inserts)

Timelapse photos of the output of the Mighty Ramp.

FAQ & Troubleshooting

Setting up the driver without an oscilloscope

The Mighty Ramp does not require an oscilloscope in order to set the required thresholds for OCP, UVLO, and the injection locked oscillator. Instead, a digital multimeter (DMM) can be used to measure the voltage at each test point. I recommend a DMM that also has a frequency measurement option for setting the injection locked oscillator frequency.

Some DMMs might not be as accurate for setting the oscillator frequency compared to an oscilloscope, but getting the exact frequency is not required. As long as the frequency is close to (slightly above or below) the secondary's resonant frequency, fine adjustment is not required.

Note: An example of using a cheap DMM (Kaiweets HT118A Digital Multimeter) to measure oscillator frequency. The oscillator is running at 402kHz per my oscilloscope, so this is plenty accurate.

Thank you for trying out the Mighty Ramp!

I will be adding another page for the Mighty Ramp half bridge in the future. Please check back.

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